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Disambiguation of "Ishikuro, Hiroki"

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Analysis and Design of an 8.5-Gb/s/Link Multi-Drop Bus Using Energy-Equipartitioned Transmission Line Couplers.

, , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (8): 2122-2131 (2015)

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Hiroki Takahashi

Hiroki Kawamura

Hiroki Sumizawa

 

Other publications of authors with the same name

A 1.26mW/Gbps 8 locking cycles versatile all-digital CDR with TDC combined DLL., , , and . ISCAS, page 1576-1579. IEEE, (2013)A 0.7V 4.1mW 850Mbps/ch inductive-coupling transceiver with adaptive pulse width controller in 65nm CMOS., , , , and . RWS, page 71-74. IEEE, (2012)0.5 V multi-phase digital controlled oscillator with smooth phase transition circuit., , , , and . APCCAS, page 232-235. IEEE, (2010)A 24mW 5.5Gbps dual frequency conversion demodulator for impulse-radio with first sidelobe., , and . RWS, page 10-12. IEEE, (2016)A 0.15-mm-Thick Noncontact Connector for MIPI Using a Vertical Directional Coupler., , , , , , , and . IEEE J. Solid State Circuits, 49 (1): 223-231 (2014)A Digital-to-Resistance Converter with an Automatic Offset Calibration Method for Evaluating Dynamic Performance of Resistive Sensor Readout Circuits., , and . I2MTC, page 1-5. IEEE, (2020)A Wide Input-Range, Low-Power and Highly Flexible 18 Bit Time-to-Digital Converter with Compact Differential Circuit Topology., and . MWSCAS, page 937-940. IEEE, (2020)A 4.6-400 K Functional Ringamp-Based 250 MS/s 12 b Pipelined ADC With PVT-Robust Unity-Gain-Frequency-Aware Bias Calibration., , , and . IEEE J. Solid State Circuits, 59 (3): 740-752 (March 2024)An Outside-Rail Opamp Design Relaxing Low-Voltage Constraint on Future Scaled Transistors., , , , and . IEICE Trans. Electron., 90-C (4): 786-792 (2007)A 4-10 bit, 0.4-1 V Power Supply, Power Scalable Asynchronous SAR-ADC in 40 nm-CMOS with Wide Supply Voltage Range SAR Controller., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 96-A (2): 443-452 (2013)