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BLoG: post-silicon bug localization in processors using bug localization graphs., , , and . DAC, page 368-373. ACM, (2010)Test Generation Methods for Utilization Improvement of Hardware-Accelerated Simulation Platforms., , , , , , , , and . IEEE Des. Test, 34 (1): 65-76 (2017)Post-Silicon Bug Localization in Processors Using Instruction Footprint Recording and Analysis (IFRA)., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 28 (10): 1545-1558 (2009)Robust System Design., , , , , , , , , and 4 other author(s). IPSJ Trans. Syst. LSI Des. Methodol., (2011)IFRA: Post-silicon bug localization in processors., and . HLDVT, page 154-159. IEEE Computer Society, (2009)IFRA: instruction footprint recording and analysis for post-silicon bug localization in processors., and . DAC, page 373-378. ACM, (2008)QED: Quick Error Detection tests for effective post-silicon validation., , , , , , , , , and . ITC, page 154-163. IEEE Computer Society, (2010)Comparative study of test generation methods for simulation accelerators., , , , , , , , and . DATE, page 321-324. ACM, (2015)Register pointer architecture for efficient embedded processors., , , , , and . DATE, page 600-605. EDA Consortium, San Jose, CA, USA, (2007)Post-silicon bug localization for processors using IFRA., and . Commun. ACM, 53 (2): 106-113 (2010)