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Steep switching tunnel FET: A promise to extend the energy efficient roadmap for post-CMOS digital and analog/RF applications., , and . ISLPED, page 145-150. IEEE, (2013)Low-Power, Adaptive Neuromorphic Systems: Recent Progress and Future Directions., , , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 8 (1): 6-27 (2018)A Uniform Latency Model for DNN Accelerators with Diverse Architectures and Dataflows., , , , , and . DATE, page 220-225. IEEE, (2022)Co-Optimization of SRAM Circuits with Sequential Access Patterns in a 7nm SoC Achieving 58% Memory Energy Reduction for AR Applications., , , , , , , and . VLSI Technology and Circuits, page 216-217. IEEE, (2022)11.2 A 3D integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at <2μm Pitch with up to 40% Energy Reduction at Iso-Area Footprint., , , , , , , , , and 3 other author(s). ISSCC, page 210-212. IEEE, (2024)Independently-Controlled-Gate FinFET 6T SRAM Cell Design for Leakage Current Reduction and Enhanced Read Access Speed., , , , , , , and . ISVLSI, page 296-301. IEEE Computer Society, (2014)Analog Circuit Design Using Tunnel-FETs., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (1): 39-48 (2015)Tunnel FET RF Rectifier Design for Energy Harvesting Applications., , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 4 (4): 400-411 (2014)Scalable energy-efficient magnetoelectric spin-orbit logic., , , , , , , , , and . Nat., 565 (7737): 35-42 (2019)Low-power high-speed current mode logic using Tunnel-FETs., , , and . VLSI-SoC, page 1-6. IEEE, (2014)