Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

19.1 A 0.5-to-9.5GHz 1.2µs-lock-time fractional-N DPLL with ±1.25% UI period jitter in 16nm CMOS for dynamic frequency and core-count scaling in SoC.

F. Ahmad, G. Unruh, A. Iyer, P. Su, S. Abdalla, B. Shen, M. Chambers, and I. Fujimori. ISSCC, page 324-325. IEEE, (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Greg Breinholt

Greg Little

Greg Ross

Greg Kiss

Greg Foderaro

Other publications of authors with the same name

A 2.7GHz to 7GHz fractional-N LCPLL utilizing multimetal layer SoC technology in 28nm CMOS.C. Lee, L. Kabalican, Y. Ge, H. Kwantono, G. Unruh, M. Chambers, and I. Fujimori. VLSIC, page 1-2. IEEE, (2014)26.6 A 5GS/S 150mW 10b SHA-less pipelined/SAR hybrid ADC in 28nm CMOS.M. Brandolini, Y. Shin, K. Raviprakash, T. Wang, R. Wu, H. Geddada, Y. Ko, Y. Ding, C. Huang, W. Shih and 13 other author(s). ISSCC, page 1-3. IEEE, (2015)19.1 A 0.5-to-9.5GHz 1.2µs-lock-time fractional-N DPLL with ±1.25% UI period jitter in 16nm CMOS for dynamic frequency and core-count scaling in SoC.F. Ahmad, G. Unruh, A. Iyer, P. Su, S. Abdalla, B. Shen, M. Chambers, and I. Fujimori. ISSCC, page 324-325. IEEE, (2016)A 19 mW/lane Serdes transceiver for SFI-5.1 application.S. Fallahi, D. Cui, D. Pi, R. Zhu, G. Unruh, M. Lugthart, and A. Momtaz. CICC, page 1-4. IEEE, (2011)A 16b 6GS/S nyquist DAC with IMD <-90dBc up to 1.9GHz in 16nm CMOS.C. Lin, J. Wong, T. Kim, G. Xie, D. Major, G. Unruh, S. Dommaraju, H. Eberhart, and A. Venes. ISSCC, page 360-362. IEEE, (2018)A 2.7 GHz to 7 GHz Fractional-N LC-PLL Utilizing Multi-Metal Layer SoC Technology in 28 nm CMOS.C. Lee, L. Kabalican, Y. Ge, H. Kwantono, G. Unruh, M. Chambers, and I. Fujimori. IEEE J. Solid State Circuits, 50 (4): 856-866 (2015)A 0.5-9.5-GHz, 1.2-µs Lock-Time Fractional-N DPLL With ±1.25%UI Period Jitter in 16-nm CMOS for Dynamic Frequency and Core-Count Scaling.F. Ahmad, G. Unruh, A. Iyer, P. Su, S. Abdalla, B. Shen, M. Chambers, and I. Fujimori. IEEE J. Solid State Circuits, 52 (1): 21-32 (2017)27.6 A 4GS/s 13b pipelined ADC with capacitor and amplifier sharing in 16nm CMOS.J. Wu, A. Chou, T. Li, R. Wu, T. Wang, G. Cusmai, S. Lin, C. Yang, G. Unruh, S. Dommaraju and 13 other author(s). ISSCC, page 466-467. IEEE, (2016)A 180 mW multistandard TV tuner in 28 nm CMOS.J. Xiao, W. Gao, X. Xu, D. Chang, J. Cao, R. Sun, V. Periasamy, N. Wang, X. Chen, G. Unruh and 10 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)

BibSonomy

Disambiguation of "Unruh, Greg"

Please choose a person to relate this publication to

Greg Breinholt

Greg Little

Greg Ross

Greg Kiss

Greg Foderaro

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Unruh, Greg"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 19.1 A 0.5-to-9.5GHz 1.2µs-lock-time fractional-N DPLL with ±1.25% UI period jitter in 16nm CMOS for dynamic frequency and core-count scaling in SoC.

Please choose a person to relate this publication to

Greg Breinholt

Greg Little

Greg Ross

Greg Kiss

Greg Foderaro

Other publications of authors with the same name

Disambiguation