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Disambiguation of "Cestero, Alberto"

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A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access.

, , , , , , , , , , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 51 (1): 230-239 (2016)

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Alberto Moreira

Alberto Coda

Alberto Ricco

Alberto Fierro

Alberto Moreira

 

Other publications of authors with the same name

A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access., , , , , , , , , and 12 other author(s). IEEE J. Solid State Circuits, 51 (1): 230-239 (2016)Field Tolerant Dynamic Intrinsic Chip ID Using 32 nm High-K/Metal Gate SOI Embedded DRAM., , , , , , and . IEEE J. Solid State Circuits, 48 (4): 940-947 (2013)An 800-MHz embedded DRAM with a concurrent refresh mode., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 40 (6): 1377-1387 (2005)A Self-Authenticating Chip Architecture Using an Intrinsic Fingerprint of Embedded DRAM., , , , , and . IEEE J. Solid State Circuits, 48 (11): 2934-2943 (2013)80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity., , , , , , , , , and 4 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)Electrically Programmable Fuse (eFUSE): From Memory Redundancy to Autonomic Chips., , , , , , , , , and . CICC, page 799-804. IEEE, (2007)3D-Split SRAM: Enabling Generational Gains in Advanced CMOS., , , , , , , , , and 6 other author(s). CICC, page 1-2. IEEE, (2021)80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 53 (3): 949-960 (2018)Dynamic intrinsic chip ID using 32nm high-K/metal gate SOI embedded DRAM., , , , , and . VLSIC, page 146-147. IEEE, (2012)