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Disambiguation of "De, Vivek"

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A 4fJ/bit delay-hardened physically unclonable function circuit with selective bit destabilization in 14nm tri-gate CMOS.

, , , , , , , , , and . VLSI Circuits, page 1-2. IEEE, (2016)

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Nagarajavel Vivekananthan

Vivek Venkataramani

Vivek Ramamurthy

Vivek Bose

Vivek Shetty

 

Other publications of authors with the same name

A 128b AES Engine with Higher Resistance to Power and Electromagnetic Side-Channel Attacks Enabled by a Security-Aware Integrated All-Digital Low-Dropout Regulator., , , , , and . ISSCC, page 404-406. IEEE, (2019)Reducing the data switching activity of serialized datastreams., , , and . ISCAS, IEEE, (2006)F3: Beyond the horizon of conventional computing: From deep learning to neuromorphic systems., , , , , and . ISSCC, page 506-508. IEEE, (2017)Mixed-Vth (MVT) CMOS Circuit Design Methodology for Low Power Applications., , , , and . DAC, page 430-435. ACM Press, (1999)Near-threshold voltage design in nanoscale CMOS.. DATE, page 612. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Monolithic voltage conversion in low-voltage CMOS technologies., , , and . Microelectron. J., 36 (9): 863-867 (2005)Energy-Efficient Computing in Nanoscale CMOS.. IEEE Des. Test, 33 (2): 68-75 (2016)Intrinsic MOSFET parameter fluctuations due to random dopant placement., , and . IEEE Trans. Very Large Scale Integr. Syst., 5 (4): 369-376 (1997)Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor., , , and . IEEE Trans. Very Large Scale Integr. Syst., 11 (3): 514-522 (2003)A Digitally Controlled Fully Integrated Voltage Regulator With On-Die Solenoid Inductor With Planar Magnetic Core in 14-nm Tri-Gate CMOS., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 53 (1): 8-19 (2018)