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Disambiguation of "Liang, Joshua"

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6.7 A 28Gb/s digital CDR with adaptive loop gain for optimum jitter tolerance.

, , , , and . ISSCC, page 122-123. IEEE, (2017)

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Liang Liang

Joshua Migdal

Joshua Sempebwa

Joshua Cordes

Joshua Amavi

 

Other publications of authors with the same name

Jitter injection for on-chip jitter measurement in PI-based CDRs., , , and . CICC, page 1-4. IEEE, (2017)On-Chip Measurement of Clock and Data Jitter With Sub-Picosecond Accuracy for 10 Gb/s Multilane CDRs., , , , and . IEEE J. Solid State Circuits, 50 (4): 845-855 (2015)A Blind Baud-Rate ADC-Based CDR., , , , and . IEEE J. Solid State Circuits, 48 (12): 3285-3295 (2013)On-chip measurement of data jitter with sub-picosecond accuracy for 10Gb/s multilane CDRs., , , , and . VLSIC, page 1-2. IEEE, (2014)A 3x blind ADC-based CDR for a 20 dB loss channel., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (6): 1658-1667 (2015)6.6 A 22.5-to-32Gb/s 3.2pJ/b referenceless baud-rate digital CDR with DFE and CTLE in 28nm CMOS., , , , , , and . ISSCC, page 120-121. IEEE, (2017)6.7 A 28Gb/s digital CDR with adaptive loop gain for optimum jitter tolerance., , , , and . ISSCC, page 122-123. IEEE, (2017)A frequency-scalable 15-bit incremental ADC for low power sensor applications., and . ISCAS, page 2418-2421. IEEE, (2010)A 22.5-to-32-Gb/s 3.2-pJ/b Referenceless Baud-Rate Digital CDR With DFE and CTLE in 28-nm CMOS., , , , , , and . IEEE J. Solid State Circuits, 52 (12): 3517-3531 (2017)Design Considerations for Time-Modulated Injection-Locked Phase Interpolators and Rotators., , and . ISCAS, page 1719-1723. IEEE, (2022)