( en | de | ru )

 

Disambiguation of "Mahmoodi-Meimand, Hamid"

Author of the publication

copydeleteadd this publication to your clipboard
Data-retention flip-flops for power-down applications.

, and . ISCAS (2), page 677-680. IEEE, (2004)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Benjamin Mahmoodi

Mehrdad Mahmoodi

Zahra Hamidi

Ahmad Hamidov

Saeed Hamid-Khani

 

Other publications of authors with the same name

Efficient power clock generation for adiabatic logic., and . ISCAS (4), page 642-645. IEEE, (2001)A process-tolerant cache architecture for improved yield in nanoscale technologies., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 13 (1): 27-38 (2005)Leakage Current in Deep-Submicron CMOS Circuits., , and . J. Circuits Syst. Comput., 11 (6): 575-600 (2002)Dual-edge triggered level converting flip-flops., and . ISCAS (2), page 661-664. IEEE, (2004)A novel synthesis approach for active leakage power reduction using dynamic supply gating., , , , and . DAC, page 479-484. ACM, (2005)Energy recovery clocked dynamic logic., , , and . ACM Great Lakes Symposium on VLSI, page 468-471. ACM, (2005)A Novel Low-Power Scan Design Technique Using Supply Gating., , , , and . ICCD, page 60-65. IEEE Computer Society, (2004)Low power synthesis of dynamic logic circuits using fine-grained clock gating., , , and . DATE, page 862-867. European Design and Automation Association, Leuven, Belgium, (2006)Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations., , , and . IEEE Trans. Very Large Scale Integr. Syst., 13 (11): 1286-1295 (2005)Data-retention flip-flops for power-down applications., and . ISCAS (2), page 677-680. IEEE, (2004)