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An OpenCL software compilation framework targeting an SoC-FPGA VLIW chip multiprocessor.

, and . J. Syst. Archit., (2016)

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Design and Implementation of a High-Performance and Silicon Efficient Arithmetic Coding Accelerator for the H.264 Advanced Video Codec., and . ASAP, page 411-416. IEEE Computer Society, (2005)High Performance 16K, 64K, 256K complex points VLSI Systolic FFT Architectures., , , , and . ICECS, page 146-149. IEEE, (2007)Hardware implementation of a novel genetic algorithm., , and . Neurocomputing, 71 (1-3): 95-106 (2007)Architecture, performance modeling and VLSI implementation methodologies for ASIC vector processors: A case study in telephony workloads., , , , and . Microprocess. Microsystems, 37 (8-D): 1122-1143 (2013)A code compression scheme for improving SoC performance., , , and . SoC, page 35-40. IEEE, (2003)Autonomous Design in VLSI: Growing and Learning on Silicon., , and . ISVLSI, page 481-485. IEEE Computer Society, (2010)High-performance arithmetic coding VLSI macro for the H264 video compression standard., and . IEEE Trans. Consumer Electronics, 51 (1): 144-151 (2005)An OpenCL software compilation framework targeting an SoC-FPGA VLIW chip multiprocessor., and . J. Syst. Archit., (2016)Fully Systolic FFT Architecture for Giga-sample Applications., , , , , and . J. Signal Process. Syst., 58 (3): 281-299 (2010)A configurable length, Fused Multiply-Add floating point unit for a VLIW processor., , and . SoCC, page 93-96. IEEE, (2009)