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A 3.14 um2 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture.

, , , , , , , and . VLSIC, page 44-45. IEEE, (2012)

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A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing., , , , , , , , , and 5 other author(s). ISCAS, page 1588-1591. IEEE, (2014)Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 50 (2): 476-489 (2015)A 16-Mb Toggle MRAM With Burst Modes., , , , , , , , , and 13 other author(s). IEEE J. Solid State Circuits, 42 (11): 2378-2385 (2007)A 3.14 um2 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture., , , , , , , and . VLSIC, page 44-45. IEEE, (2012)Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating., , , , , , , , , and 4 other author(s). ISSCC, page 194-195. IEEE, (2013)Fabrication of a magnetic tunnel junction-based 240-tile nonvolatile field-programmable gate array chip skipping wasted write operations for greedy power-reduced logic applications., , , , , , , , , and 1 other author(s). IEICE Electron. Express, 10 (23): 20130772 (2013)10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications., , , , , , , , , and 4 other author(s). ISSCC, page 184-185. IEEE, (2014)1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times., , , , , , , , and . VLSIC, page 46-47. IEEE, (2012)A 90nm 12ns 32Mb 2T1MTJ MRAM., , , , , , , , , and 10 other author(s). ISSCC, page 462-463. IEEE, (2009)Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure., , , , , , , , , and 1 other author(s). VLSIC, page 172-. IEEE, (2015)