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Disambiguation of "Goh, Wang Ling"

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A 0.7V 24µA Hybrid OTA Driving 15 nF Capacitive Load With 1.46 MHz GBW.

, , , , , , and . IEEE J. Solid State Circuits, 50 (11): 2750-2757 (2015)

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Ling Wang

Chen-Ling Wang

Ching-Ling Wang

Yan-Ling Wang

Hanlin Goh

 

Other publications of authors with the same name

A novel FPGA implementation of mirror-paradigm RS-based QC-LDPC decoder for NVM channels., , and . ISPACS, page 760-765. IEEE, (2012)A three-topology based, wide input range switched-capacitor DC-DC converter with low-ripple and enhanced load line regulations., , and . ISIC, page 13-16. IEEE, (2014)A Dual-Feedforward Carrier-Modulated Second-Order Class-D Amplifier With Improved THD., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 59-II (1): 35-39 (2012)A 3-MHz 17.3- $\mu$ W 0.015% Period Jitter Relaxation Oscillator With Energy Efficient Swing Boosting., , and . IEEE Trans. Circuits Syst. II Express Briefs, 67-II (10): 1745-1749 (2020)A passively compensated capacitive sensor readout with biased varactor temperature compensation and temperature coherent quantization., , , , , and . ISCAS, page 1-4. IEEE, (2017)A Low-Cost High-Throughput Digital Design of Biorealistic Spiking Neuron., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 68 (4): 1398-1402 (2021)A Low Power and Low Area Router With Congestion-Aware Routing Algorithm for Spiking Neural Network Hardware Implementations., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 68 (1): 471-475 (2021)Enhanced active-feedback frequency compensation with on-chip-capacitor reduction feature for amplifiers with large capacitive load., , , , and . Int. J. Circuit Theory Appl., 45 (12): 2119-2133 (2017)A Ternary Weight Mapping and Charge-mode Readout Scheme for Energy Efficient FeRAM Crossbar Compute-in-Memory System., , , , , and . AICAS, page 1-5. IEEE, (2023)A Battery-input Hysteretic Buck Converter with 430nA Quiescent Current and 5×104 Load Current Dynamic Range for Wearable Biomedical Devices., , , and . BioCAS, page 1-5. IEEE, (2023)