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A Configurable and Strong RAS Solution for Die-Stacked DRAM Caches., , , and . IEEE Micro, 34 (3): 80-90 (2014)Soteria: Towards Resilient Integrity-Protected and Encrypted Non-Volatile Memories., , , and . MICRO, page 1214-1226. ACM, (2021)Eliminating microarchitectural dependency from Architectural Vulnerability., and . HPCA, page 117-128. IEEE Computer Society, (2009)Resilient die-stacked DRAM caches., , , and . ISCA, page 416-427. ACM, (2013)Nonblocking DRAM Refresh., , , , and . IEEE Micro, 39 (3): 103-109 (2019)Lessons learned from memory errors observed over the lifetime of Cielo., , , , , and . SC, page 43:1-43:12. IEEE / ACM, (2018)Reducing Data Cache Susceptibility to Soft Errors., , , and . IEEE Trans. Dependable Secur. Comput., 3 (4): 353-364 (2006)A Research Retrospective on AMD's Exascale Computing Journey., , , , , , , , , and 61 other author(s). ISCA, page 81:1-81:14. ACM, (2023)Assessing the impact of hard faults in performance components of modern microprocessors., , , and . ICCD, page 207-214. IEEE Computer Society, (2013)Vulnerability analysis of L2 cache elements to single event upsets., , , and . DATE, page 1276-1281. European Design and Automation Association, Leuven, Belgium, (2006)