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Disambiguation of "Diessel, Oliver"

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Significant papers from the first 25 years of the FPL conference.

, , , , , , , , , , , , , , , , and . FPL, page 1-3. IEEE, (2015)

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Franz Dießel

Alfred Diessel

Holger Diessel

Thomas Diessel

Joachim Diessel

 

Other publications of authors with the same name

Partial FPGA Rearrangement by Local Repacking (Abstract)., and . FPGA, page 259. ACM, (1998)Configuration Merging in Point-to-Point Networks for Module-Based FPGA Reconfiguration., and . ACM Trans. Reconfigurable Technol. Syst., 3 (1): 4:1-4:36 (2010)Fine-grained module-based error recovery in FPGA-based TMR systems., , , , and . FPT, page 101-108. IEEE, (2016)Scheduling Considerations for Voter Checking in TMR-MER Systems., , and . FCCM, page 30. IEEE Computer Society, (2017)TLegUp: A TMR Code Generation Tool for SRAM-Based FPGA Applications Using HLS., , , , and . FCCM, page 129-132. IEEE Computer Society, (2017)A Configuration Memory Architecture for Fast Run-Time-Reconfiguration of FPGAs., and . FPL, page 636-639. IEEE, (2005)Efficient Fine-grained Processor-logic Interactions on the Cache-coherent Zynq Platform., and . ACM Trans. Reconfigurable Technol. Syst., 11 (4): 25:1-25:22 (2019)Dynamic scheduling of voter checks in FPGA-based TMR systems., , , and . FPT, page 169-172. IEEE, (2016)Functional Unit Chaining: A Runtime Adaptive Architecture for Reducing Bypass Delays., and . Asia-Pacific Computer Systems Architecture Conference, volume 4186 of Lecture Notes in Computer Science, page 161-174. Springer, (2006)Compiling Process Algebraic Descriptions into Reconfigurable Logic., and . IPDPS Workshops, volume 1800 of Lecture Notes in Computer Science, page 916-923. Springer, (2000)