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Disambiguation of "Alioto, Massimo"

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Beyond Ideal DVFS Through Ultra-Fine Grain Vdd-Hopping.

, , , , and . VLSI-SoC (Selected Papers), volume 508 of IFIP Advances in Information and Communication Technology, page 152-172. Springer, (2016)

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Massimo Viola

Massimo Tallarida

Massimo Malagó

Massimo Moser

Massimo Busin

 

Other publications of authors with the same name

26.3 Reconfigurable clock networks for random skew mitigation from subthreshold to nominal voltage., , and . ISSCC, page 440-441. IEEE, (2017)A general model for differential power analysis attacks to static logic circuits., , and . ISCAS, page 3346-3349. IEEE, (2008)Metrics and Design Considerations on the Energy-delay Tradeoff of Digital Circuits., , and . ISCAS, page 3150-3153. IEEE, (2009)A gate-level strategy to design Carry Select Adders., , and . ISCAS (2), page 465-468. IEEE, (2004)EQSCALE: Energy-quality scalable feature extraction engine for Sub-mW real-time video processing with 0.55 mm2 area in 40nm CMOS., , and . A-SSCC, page 241-244. IEEE, (2017)A 595pW 14pJ/Cycle microcontroller with dual-mode standard cells and self-startup for battery-indifferent distributed sensing., , and . ISSCC, page 44-46. IEEE, (2018)17.3 A reconfigurable dual-port memory with error detection and correction in 28nm FDSOI., , , , , and . ISSCC, page 310-312. IEEE, (2016)Power-delay optimization of D-latch/MUX source coupled logic gates., and . I. J. Circuit Theory and Applications, 33 (1): 65-86 (2005)Drop-In Energy-Performance Range Extension in Microcontrollers Beyond VDD Scaling., , and . A-SSCC, page 125-128. IEEE, (2019)Power-Aware Design of Nanometer MCML Tapered Buffers., and . IEEE Trans. Circuits Syst. II Express Briefs, 55-II (1): 16-20 (2008)