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A 1-to-6Gb/s phase-interpolator-based burst-mode CDR in 65nm CMOS., , , , and . ISSCC, page 154-156. IEEE, (2011)A pattern-guided adaptive equalizer in 65nm CMOS., , , , and . ISSCC, page 354-356. IEEE, (2011)On-chip measurement of data jitter with sub-picosecond accuracy for 10Gb/s multilane CDRs., , , , and . VLSIC, page 1-2. IEEE, (2014)A Continuous-Time 0-3 MASH ADC Achieving 88 dB DR With 53 MHz BW in 28 nm CMOS., , , , and . IEEE J. Solid State Circuits, 49 (12): 2868-2877 (2014)A 3x blind ADC-based CDR for a 20 dB loss channel., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (6): 1658-1667 (2015)Content-addressable memory (CAM) circuits and architectures: a tutorial and survey., and . IEEE J. Solid State Circuits, 41 (3): 712-727 (2006)A ternary content-addressable memory (TCAM) based on 4T static storage and including a current-race sensing scheme., , and . IEEE J. Solid State Circuits, 38 (1): 155-158 (2003)Jump Markov chains and rejection-free Metropolis algorithms., , , , , and . Comput. Stat., 36 (4): 2789-2811 (2021)Design and Implementation of an On-Demand Maximum-Likelihood Sequence Estimation (MLSE)., , , , and . IEEE Open J. Circuits Syst., (2022)Real-time sound localization using field-programmable gate arrays., , and . ICME, page 829-832. IEEE Computer Society, (2003)