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Disambiguation of "Lee, Sangpil"

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Warped-preexecution: A GPU pre-execution approach for improving latency hiding.

, , , , , and . HPCA, page 163-175. IEEE Computer Society, (2016)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Xavier Lee Lee

Bongsoo Lee

The role of negative regulators in coordination of the Myxococcus xanthus developmental program. Uni Marburg, (2009)

Min-Hi Lee

Induction and regulation of antiviral defence mechanisms through intracytoplasmic sensors. HU Berlin, (2009)

Kishik Lee

Sunhee Lee

 

Other publications of authors with the same name

DRAW: investigating benefits of adaptive fetch group size on GPU., , , , , and . ISPASS, page 183-192. IEEE Computer Society, (2015)Accelerated Network Coding with Dynamic Stream Decomposition on Graphics Processing Unit., and . Comput. J., 55 (1): 21-34 (2012)An Efficient Block Cipher Implementation on Many-Core Graphics Processing Units., , , and . J. Inf. Process. Syst., 8 (1): 159-174 (2012)Parallelized sub-resource loading for web rendering engine., , , and . J. Syst. Archit., 59 (9): 785-793 (2013)Dynamic Resizing on Active Warps Scheduler to Hide Operation Stalls on GPUs., , , , , and . IEEE Trans. Parallel Distributed Syst., 28 (11): 3142-3156 (2017)Improving Energy Efficiency of GPUs through Data Compression and Compressed Execution., , , , , and . IEEE Trans. Computers, 66 (5): 834-847 (2017)In vivo detection of gray and white matter differences in GABA concentration in the human brain., , , and . NeuroImage, 33 (1): 85-93 (2006)Parallel GPU architecture simulation framework exploiting work allocation unit parallelism., and . ISPASS, page 107-117. IEEE Computer Society, (2013)Warped-preexecution: A GPU pre-execution approach for improving latency hiding., , , , , and . HPCA, page 163-175. IEEE Computer Society, (2016)Parallel GPU Architecture Simulation Framework Exploiting Architectural-Level Parallelism with Timing Error Prediction., and . IEEE Trans. Computers, 65 (4): 1253-1265 (2016)