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A Pipeline Design of a Fast Prime Factor DFT on a Finite Field.

, , , , and . IEEE Trans. Computers, 37 (3): 266-273 (1988)

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A Pipeline Design of a Fast Prime Factor DFT on a Finite Field., , , , and . IEEE Trans. Computers, 37 (3): 266-273 (1988)The VLSI Implementation of a Reed-Solomon Encoder Using Berlekamp's Bit-Serial Multiplier Algorithm., , , , , and . IEEE Trans. Computers, 33 (10): 906-911 (1984)An FPT algorithm with a modularized structure for computing 2-D cyclic convolutions., , , , and . IEEE Trans. Acoust. Speech Signal Process., 36 (9): 1540-1542 (1988)Techniques for Computing the Discrete Fourier Transform Using the Quadratic Residue Fermat Number Systems., , , , and . IEEE Trans. Computers, 35 (11): 1008-1012 (1986)The VLSI design of a single chip for the multiplication of integers modulo a fermat number., , , , and . ICASSP, page 1388-1391. IEEE, (1985)A single chip VLSI Reed-Solomon decoder., , , , and . ICASSP, page 2151-2154. IEEE, (1986)A Comparison of VLSI Architecture of Finite Field Multipliers Using Dual, Normal, or Standard Bases., , , and . IEEE Trans. Computers, 37 (6): 735-739 (1988)The VLSI Design of an Error-Trellis Syndrome Decoder for Certain Convolutional Codes., , , and . IEEE Trans. Computers, 35 (9): 781-789 (1986)A new VLSI complex integer multiplier which uses a quadratic-polynomial residue system with fermat numbers., , , , and . IEEE Trans. Acoust. Speech Signal Process., 35 (7): 1076-1079 (1987)VLSI residue multiplier modulo a Fermat number., , , , and . IEEE Symposium on Computer Arithmetic, page 203-206. IEEE, (1985)