( en | de | ru )

 

Disambiguation of "Yoshimoto, Masahiko"

Author of the publication

copydeleteadd this publication to your clipboard
Fast and Low-Memory-Bandwidth Architecture of SIFT Descriptor Generation with Scalability on Speed and Accuracy for VGA Video.

, , , , , , and . FPL, page 608-611. IEEE Computer Society, (2010)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Masahiko Isaji

Kei Yoshimoto

 

Other publications of authors with the same name

A Counter-based Read Circuit Tolerant to Process Variation for 0.4-V Operating STT-MRAM., , , , , , , and . IPSJ Trans. Syst. LSI Des. Methodol., (2016)Design Choice in 45-nm Dual-Port SRAM - 8T, 10T Single End, and 10T Differential., , , , , , and . IPSJ Trans. Syst. LSI Des. Methodol., (2011)A half-pel precision MPEG2 motion-estimation processor with concurrent three-vector search., , , , , , , , , and . IEEE J. Solid State Circuits, 30 (12): 1502-1509 (December 1995)A 28-nm 484-fJ/writecycle 650-fJ/readcycle 8T Three-Port FD-SOI SRAM for Image Processor., , , , , , and . IEICE Trans. Electron., 99-C (8): 901-908 (2016)Data Transmission Scheduling Based on RTS/CTS Exchange for Periodic Data Gathering Sensor Networks., , , , and . IEICE Trans. Commun., 90-B (12): 3410-3418 (2007)Divided Static Random Access Memory for Data Aggregation in Wireless Sensor Nodes., , , , , , , and . IEICE Trans. Commun., 95-B (1): 178-188 (2012)A Dependable SRAM with 7T/14T Memory Cells., , , , , and . IEICE Trans. Electron., 92-C (4): 423-432 (2009)A Sub 100 mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer., , , , , , , , and . IEICE Trans. Electron., 91-C (4): 465-478 (2008)VLSI Architecture of GMM Processing and Viterbi Decoder for 60, 000-Word Real-Time Continuous Speech Recognition., , , , , and . IEICE Trans. Electron., 94-C (4): 458-467 (2011)A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme., , , , , , , , and . IEICE Trans. Electron., 98-C (4): 333-339 (2015)