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Disambiguation of "Koibuchi, Michihiro"

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Performance Improvement Methodology for ClearSpeed's CSX600.

, , , , and . ICPP, page 77. IEEE Computer Society, (2007)

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Michihiro Saito

 

Other publications of authors with the same name

A link removal methodology for Networks-on-Chip on reconfigurable systems., , , and . FPL, page 269-274. IEEE, (2008)SINET5: A low-latency and high-bandwidth backbone network for SDN/NFV Era., , , , , , , , , and 1 other author(s). ICC, page 1-7. IEEE, (2017)The Impact of Application Mapping on Non-Random and Random Network Topologies., and . ISPA/BDCloud/SocialCom/SustainCom, page 16-25. IEEE, (2019)Architectural Design of Next-Generation Science Information Network., , , , , , and . IEICE Trans. Commun., 90-B (5): 1061-1070 (2007)Designing High-Performance Interconnection Networks with Host-Switch Graphs., , , , and . IEEE Trans. Parallel Distributed Syst., 30 (2): 315-330 (2019)A Switch-Tagged Routing Methodology for PC Clusters with VLAN Ethernet., , , and . IEEE Trans. Parallel Distributed Syst., 22 (2): 217-230 (2011)MMLRU Selection Function: A Simple and Efficient Output Selection Function in Adaptive Routing., , and . IEICE Trans. Inf. Syst., 88-D (1): 109-118 (2005)AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation., , , , and . NOCS, page 6:1-6:8. IEEE, (2018)A Virtual-Channel Free Mapping for Application-Specific On-Chip Torus Networks., , and . PDCS, page 24-31. ISCA, (2006)Scalable Low-Latency Inter-FPGA Networks., , , , and . IPDPS, page 234-245. IEEE, (2022)