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On hardware generation of random single input change test sequences., , , , and . ETW, page 117-123. IEEE Computer Society, (2001)Intra-Cell Defects Diagnosis., , , , , , and . J. Electron. Test., 30 (5): 541-555 (2014)Random Adjacent Sequences: An Efficient Solution for Logic BIST., , , , and . VLSI-SOC, volume 218 of IFIP Conference Proceedings, page 413-424. Kluwer, (2001)Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles., , , , and . VLSI-SoC, volume 240 of IFIP, page 267-281. Springer, (2005)A two-layer SPICE model of the ATMEL TSTACTM eFlash memory technology for defect injection and faulty behavior prediction., , , , , , , , and . European Test Symposium, page 81-86. IEEE Computer Society, (2010)Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes., , , , , , and . European Test Symposium, page 132-137. IEEE Computer Society, (2010)Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 21 (5): 958-970 (2013)Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test., , , , , and . J. Electron. Test., 21 (2): 169-179 (2005)A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction., , , , , , and . J. Electron. Test., 24 (4): 353-364 (2008)A Survey of Testing Techniques for Approximate Integrated Circuits., , , , and . Proc. IEEE, 108 (12): 2178-2194 (2020)