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Sequential circuit testability enhancement using a nonscan approach., , , and . IEEE Trans. Very Large Scale Integr. Syst., 3 (2): 333-338 (1995)Parallel construction algorithms for BDDs., and . ISCAS (1), page 318-322. IEEE, (1999)Parallel algorithms for VLSI circuit extraction., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 10 (5): 604-618 (1991)An evaluation of parallel simulated annealing strategies with application to standard cell placement., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (4): 398-410 (1997)Parallel algorithms for VLSI computer-aided design.. Prentice Hall, (1994)On the Construction of Communication Networks Satisfying Bounded Fan-In of Service Ports., and . IEEE Trans. Computers, 37 (9): 1148-1151 (1988)Parallel Algorithms for Force Directed Scheduling of Flattened and Hierarchical Signal Flow Graphs., and . IEEE Trans. Computers, 48 (7): 762-768 (1999)Efficient Techniques for the Analysis of Algorithm-Based Fault Tolerance (ABFT) Schemes., , and . IEEE Trans. Computers, 45 (4): 499-503 (1996)Performance Evaluation of Hardware Support for Message Passing in Distributed Memory Multicomputers., and . ICPP (1), page 604-607. CRC Press, (1991)An Approximate Algorithm for the Partitionable Independent Task Scheduling Problem., and . ICPP (1), page 72-75. Pennsylvania State University Press, (1990)