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Disambiguation of "Bishnoi, Rajendra"

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GREAT: HeteroGeneous IntegRated Magnetic tEchnology Using Multifunctional Standardized sTack.

, , , , , , , , , , , , , , , and . ISVLSI, page 344-349. IEEE Computer Society, (2017)

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Rajendra Bari

Rajendra Persaud

Rajendra Kumar

Rajendra Chandisingh

Rajendra Chandisingh

 

Other publications of authors with the same name

Approximate Spintronic Memories., , and . ACM J. Emerg. Technol. Comput. Syst., 16 (4): 43:1-43:22 (2020)A Lightweight Architecture for Real-Time Neuronal-Spike Classification., , , , , , , , and . CoRR, (2023)PetaOps/W edge-AI $\mu$ Processors: Myth or reality?, , , , , , , , , and 18 other author(s). DATE, page 1-6. IEEE, (2023)Reliable Low-Power High Performance Spintronic Memories. Karlsruhe University, Germany, (2017)base-search.net (ftubkarlsruhe:oai:EVASTAR-Karlsruhe.de:1000070974).Variation-Aware Physics-Based Electromigration Modeling and Experimental Calibration for VLSI Interconnects., , , , , , , and . IRPS, page 1-6. IEEE, (2019)Parametric failure modeling and yield analysis for STT-MRAM., , and . DATE, page 265-268. IEEE, (2018)Process variation and temperature aware adaptive scrubbing for retention failures in STT-MRAM., , , and . ASP-DAC, page 203-208. IEEE, (2018)Unbalanced Bit-slicing Scheme for Accurate Memristor-based Neural Network Architecture., , , , and . AICAS, page 1-4. IEEE, (2021)Defect injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAM., , , , , , and . ITC, page 1-10. IEEE, (2018)Modeling and Testing of Aging Faults in FinFET Memories for Automotive Applications., , , , , , and . ITC, page 1-10. IEEE, (2018)