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Disambiguation of "Wei, Liqiong"

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Multiple-Vdd multiple-Vth CMOS (MVCMOS) for low power applications.

, , and . ISCAS (1), page 366-370. IEEE, (1999)

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Wei Wei

Wei Wei

Wei Wei

Wei Wei

Wei Wei

 

Other publications of authors with the same name

A 3.6Mb 10.1Mb/mm2 Embedded Non-Volatile ReRAM Macro in 22nm FinFET Technology with Adaptive Forming/Set/Reset Schemes Yielding Down to 0.5V with Sensing Time of 5ns at 0.7V., , , , , , , , , and 7 other author(s). ISSCC, page 212-214. IEEE, (2019)Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits., , , , and . DAC, page 489-494. ACM Press, (1998)A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications., , , , , , , , , and 6 other author(s). ISSCC, page 324-606. IEEE, (2007)Design and optimization of dual-threshold circuits for low-voltage low-power applications., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 7 (1): 16-24 (1999)Low Voltage Low Power CMOS Design Techniques for Deep Submicron ICs., , and . VLSI Design, page 24-29. IEEE Computer Society, (2000)A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management., , , , , , , , and . ISSCC, page 456-457. IEEE, (2009)On effective IDDQ testing of low-voltage CMOS circuits using leakage control techniques., , and . IEEE Trans. Very Large Scale Integr. Syst., 9 (5): 718-725 (2001)A 1.1 GHz 12 µA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 43 (1): 172-179 (2008)Bit Cell Optimizations and Circuit Techniques for Nanoscale SRAM Design., , , , , , and . IEEE Des. Test Comput., 28 (1): 22-31 (2011)Power minimization by simultaneous dual-Vth assignment and gate-sizing., , and . CICC, page 413-416. IEEE, (2000)