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Disambiguation of "Mu, Fenghao"

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Methodology of layout based schematic and its usage in efficient high performance CMOS design.

, and . ISCAS (6), page 254-257. IEEE, (1999)

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Meiru Mu

Qipeng Mu

Xiaoke Mu

Sijia Mu

Huiying Mu

 

Other publications of authors with the same name

High speed multistage CMOS clock buffers with pulse width control loop., and . ISCAS (2), page 541-544. IEEE, (1999)Methodology of layout based schematic and its usage in efficient high performance CMOS design., and . ISCAS (6), page 254-257. IEEE, (1999)Simultaneous Reception and Scanning Using Complex IF Radio Architectures., , and . VTC Fall, page 1-5. IEEE, (2011)High speed interface for system-on-chip design by self-tested self-synchronization., and . ISCAS (2), page 516-519. IEEE, (1999)A layout-based schematic method for very high-speed CMOS cell design., and . IEEE Trans. Very Large Scale Integr. Syst., 7 (1): 144-148 (1999)Complex IF Harmonic Rejection Mixer for Non-Contiguous Dual Carrier Reception in 65 nm CMOS., , , , , , , , , and . IEEE J. Solid State Circuits, 48 (7): 1659-1668 (2013)Pulsewidth control loop in high-speed CMOS clock buffers., and . IEEE J. Solid State Circuits, 35 (2): 134-141 (2000)Complex IF harmonic rejection mixer for non-contiguous dual carrier reception in 65 nm CMOS., , , , , , , , , and . ESSCIRC, page 357-360. IEEE, (2012)Self-Synchronized Vector Transfer for High Speed Parallel Systems., and . ICPADS, page 2-9. IEEE Computer Society, (1998)Efficient High-Speed CMOS Design by Layout Based Schematic Method., and . EUROMICRO, page 10337-10340. IEEE Computer Society, (1998)