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Bounding Loop Iterations for Timing Analysis., , , and . IEEE Real Time Technology and Applications Symposium, page 12-21. IEEE Computer Society, (1998)Improving Program Efficiency by Packing Instructions into Registers., , , and . ISCA, page 260-271. IEEE Computer Society, (2005)Using de-optimization to re-optimize code., , , and . EMSOFT, page 114-123. ACM, (2005)Automatic Isolation of Compiler Errors.. ACM Trans. Program. Lang. Syst., 16 (5): 1648-1659 (1994)Supporting User-Friendly Analysis of Timing Constraints., , and . Workshop on Languages, Compilers, & Tools for Real-Time Systems, page 99-107. ACM, (1995)Improving Performance by Branch Reordering., , and . PLDI, page 130-141. ACM, (1998)Automatic Validation of Code-Improving Transformations., , and . LCTES, volume 1985 of Lecture Notes in Computer Science, page 206-210. Springer, (2000)Redesigning a tagless access buffer to require minimal ISA changes., , , , , , and . CASES, page 19:1-19:10. ACM, (2016)Optimizing Transfers of Control in the Static Pipeline Architecture., , , , and . LCTES, page 1:1-1:10. ACM, (2015)Fast context switches: compiler and architectural support for preemptive scheduling., , and . Microprocess. Microsystems, 19 (1): 35-42 (1995)