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High-density and low-leakage novel embedded 3D MIM capacitor on Si interposer.

C. Neve, M. Detalle, P. Nolmans, Y. Li, J. Vos, G. der Plas, G. Beyer, and E. Beyne. 3DIC, page 1-4. IEEE, (2016)

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Kai Marc Geertsema

Stefaan Van der Vekens

Christian van der Steeg

Christian van der Linde

Adrianus van der Hoeven

Other publications of authors with the same name

Analog-Digital Partitioning for Low-Power UWB Impulse Radios under CMOS Scaling.M. Badaroglu, C. Desset, J. Ryckaert, V. Heyn, G. der Plas, P. Wambacq, and B. van Poucke. EURASIP J. Wireless Comm. and Networking, (2006)Systematic design of a 14-bit 150-MS/s CMOS current-steering D/A converter.G. der Plas, J. Vandenbussche, W. Daems, A. van den Bosch, G. Gielen, and W. Sansen. DAC, page 452-457. ACM, (2000)A 2.2mW 5b 1.75GS/s Folding Flash ADC in 90nm Digital CMOS.B. Verbruggen, J. Craninckx, M. Kuijk, P. Wambacq, and G. der Plas. ISSCC, page 252-253. IEEE, (2008)Evolution of substrate noise generation mechanisms with CMOS technology scaling.M. Badaroglu, P. Wambacq, G. der Plas, S. Donnay, G. Gielen, and H. Man. IEEE Trans. Circuits Syst. I Regul. Pap., 53-I (2): 296-305 (2006)Impact of technology scaling on substrate noise generation mechanisms mixed signal ICs.M. Badaroglu, P. Wambacq, G. der Plas, S. Donnay, G. Gielen, and H. Man. CICC, page 501-504. IEEE, (2004)A gradient-error and edge-effect tolerant switching scheme for a high-accuracy DAC.J. Deveugele, G. der Plas, M. Steyaert, G. Gielen, and W. Sansen. IEEE Trans. Circuits Syst. I Regul. Pap., 51-I (1): 191-195 (2004)A study on substrate noise coupling among TSVs in 3D chip stack.Y. Araga, M. Nagata, J. Vos, G. der Plas, and E. Beyne. IEICE Electron. Express, 15 (13): 20180460 (2018)A 12 bit 200 MHz low glitch CMOS D/A converter.A. den Bosch, M. Borremans, J. Vandenbussche, G. der Plas, A. Marques, J. Bastos, M. Steyaert, G. Gielen, and W. Sansen. CICC, page 249-252. IEEE, (1998)Design issues in heterogeneous 3D/2.5D integration.D. Milojevic, P. Marchal, E. Marinissen, G. der Plas, D. Verkest, and E. Beyne. ASP-DAC, page 403-410. IEEE, (2013)Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance.C. Soens, G. der Plas, P. Wambacq, and S. Donnay. DATE, page 270-275. IEEE Computer Society, (2005)

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Disambiguation of "der Plas, Geert Van"

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High-density and low-leakage novel embedded 3D MIM capacitor on Si interposer.

Please choose a person to relate this publication to

Kai Marc Geertsema

Stefaan Van der Vekens

Christian van der Steeg

Christian van der Linde

Adrianus van der Hoeven

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "der Plas, Geert Van"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML High-density and low-leakage novel embedded 3D MIM capacitor on Si interposer.

Please choose a person to relate this publication to

Kai Marc Geertsema

Stefaan Van der Vekens

Christian van der Steeg

Christian van der Linde

Adrianus van der Hoeven

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

High-density and low-leakage novel embedded 3D MIM capacitor on Si interposer.