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Behavioural Scheduling to Balance the Bit-Level Computational Effort.

, , , and . ISVLSI, page 99-104. IEEE Computer Society, (2004)

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Formal Techniques for Hardware Allocation., , and . VLSI Design, page 161-165. IEEE Computer Society, (1997)Methodology for Refinement and Optimisation of Dynamic Memory Management for Embedded Systems in Multimedia Applications., , , , , , , and . VLSI Signal Processing, 40 (3): 383-396 (2005)Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis., , , and . PATMOS, volume 2799 of Lecture Notes in Computer Science, page 617-627. Springer, (2003)Efficient Verification of Scheduling, Allocation and Binding in High-Level Synthesis., , , and . DSD, page 308-315. IEEE Computer Society, (2002)Multiple-Precision Circuits Allocation Independent of Data-Objects Length., , and . DATE, page 909-913. IEEE Computer Society, (2002)Maximizing Conditonal Reuse by Pre-Synthesis Transformations., , and . DATE, page 1097. IEEE Computer Society, (2002)Pre-synthesis optimization of multiplications to improve circuit performance., , , and . DATE, page 1306-1311. European Design and Automation Association, Leuven, Belgium, (2006)Arrival time aware scheduling to minimize clock cycle length., , , and . ASP-DAC, page 1018-1021. ACM Press, (2005)Performance-driven scheduling of behavioural specifications., , , and . Integr., 42 (3): 294-303 (2009)Memory-access-aware data structure transformations for embedded software with dynamic data accesses., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 12 (3): 269-280 (2004)