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Disambiguation of "Mak, Pui-In"

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A Nonrecursive Digital Calibration Technique for Joint Elimination of Transmitter and Receiver I/Q Imbalances With Minimized Add-On Hardware.

, , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 60-II (8): 462-466 (2013)

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Ellen Mak

Beatrice Puiu

Rebecca Mak

Kwok Mak

Ale PuÌ

 

Other publications of authors with the same name

Micropower two-stage amplifier employing recycling current-buffer Miller compensation., , , , and . ISCAS, page 1889-1892. IEEE, (2014)26.9 A 0.038mm2 SAW-less multiband transceiver using an N-Path SC gain loop., , and . ISSCC, page 452-454. IEEE, (2016)An open-source-input, ultra-wideband LNA with mixed-voltage ESD protection for full-band (170-to-1700 MHz) mobile TV tuners., , and . ISCAS, page 668-671. IEEE, (2008)A single-to-differential LNA topology with robust output gain-phase balancing against balun imbalance., , and . ISCAS, page 289-292. IEEE, (2011)Energy Optimized Subthreshold VLSI Logic Family With Unbalanced Pull-Up/Down Network and Inverse Narrow-Width Techniques., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (12): 3119-3123 (2015)A 0.0045-mm2 32.4-µW Two-Stage Amplifier for pF-to-nF Load Using CM Frequency Compensation., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 62-II (3): 246-250 (2015)A Hardware-Efficient Feedback Polynomial Topology for DPD Linearization of Power Amplifiers: Theory and FPGA Validation., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (9): 2889-2902 (2018)A 36-Gb/s 1.3-mW/Gb/s Duobinary-Signal Transmitter Exploiting Power-Efficient Cross-Quadrature Clocking Multiplexers With Maximized Timing Margin., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (9): 3014-3026 (2018)A 0.46-mm 2 4-dB NF Unified Receiver Front-End for Full-Band Mobile TV in 65-nm CMOS., and . IEEE J. Solid State Circuits, 46 (9): 1970-1984 (2011)A 0.038-mm2 SAW-Less Multiband Transceiver Using an N-Path SC Gain Loop., , and . IEEE J. Solid State Circuits, 52 (8): 2055-2070 (2017)