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Session 8 overview: Low-power digital circuits., and . ISSCC, page 144-145. IEEE, (2016)3.1 POWER9™: A processor family optimized for cognitive computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4., , , , , , , , , and 4 other author(s). ISSCC, page 50-51. IEEE, (2017)Physical design and implementation of POWER8™ (P8) server class processor., , , and . MWSCAS, page 1-4. IEEE, (2015)F3: Adaptive design techniques for energy efficiency., , , , , and . ISSCC, page 514-515. IEEE, (2014)Session 3 overview: Processors., and . ISSCC, page 44-45. IEEE, (2013)Design of the Power6 Microprocessor., , , , , , , , , and 7 other author(s). ISSCC, page 96-97. IEEE, (2007)The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4., , , , , , , , , and 13 other author(s). IEEE J. Solid State Circuits, 53 (1): 91-101 (2018)POWER10™: A 16-Core SMT8 Server Processor With 2TB/s Off-Chip Bandwidth in 7nm Technology., , , , , , , , , and 2 other author(s). ISSCC, page 48-50. IEEE, (2022)POWER8 design methodology innovations for improving productivity and reducing power., , , , , , , , , and 1 other author(s). CICC, page 1-9. IEEE, (2014)F6: I/O design at 25Gb/s and beyond: Enabling the future communication infrastructure for big data., , , , , and . ISSCC, page 1-2. IEEE, (2015)