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Disambiguation of "Raghavan, Praveen"

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Comparative BTI analysis for various sense amplifier designs.

, , , , , , and . DDECS, page 68-73. IEEE, (2016)

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Raghavan Vallur

Praveen Konidala

Paurush Praveen

Sarada Raghavan

Raghavan Chinnadurai

 

Other publications of authors with the same name

Coarse-Grained Reconfigurable Array Architectures., , and . Handbook of Signal Processing Systems, Springer, (2013)Dimensioning for power and performance under 10nm: The limits of FinFETs scaling., , , , , , , and . ICICDT, page 1-4. IEEE, (2015)Modeling FinFET metal gate stack resistance for 14nm node and beyond., , , , , , , , and . ICICDT, page 1-4. IEEE, (2015)Bias Temperature Instability analysis of FinFET based SRAM cells., , , , , , and . DATE, page 1-6. European Design and Automation Association, (2014)Resolving the memory bottleneck for single supply near-threshold computing., , , , , and . DATE, page 1-6. European Design and Automation Association, (2014)A Customized Cross-Bar for Data-Shuffling in Domain-Specific SIMD Processors., , , , , , and . ARCS, volume 4415 of Lecture Notes in Computer Science, page 57-68. Springer, (2007)A Novel Nondestructive Bit-Line Discharging Scheme for Deep Submicrometer STT-RAMs., , , and . IEEE Trans. Emerg. Top. Comput., 7 (2): 294-300 (2019)Low-leakage sub-threshold 9 T-SRAM cell in 14-nm FinFET technology., , , and . Int. J. Circuit Theory Appl., 45 (11): 1647-1659 (2017)Locality optimization in a compiler for wireless applications., , , , , and . Des. Autom. Embed. Syst., 13 (1-2): 53-72 (2009)MILP-Based Optimization of 2-D Block Masks for Timing-Aware Dummy Segment Removal in Self-Aligned Multiple Patterning Layouts., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (7): 1075-1088 (2017)