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Toward a scalable test methodology for 2D-mesh Network-on-Chips.

, and . DATE, page 367-372. EDA Consortium, San Jose, CA, USA, (2007)

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From Simulink to NoC-based MPSoC on FPGA., and . DATE, page 1-4. European Design and Automation Association, (2014)Mitigating single-event upsets in COTS SDRAM using an EDAC SDRAM controller., , and . NORCAS, page 1-6. IEEE, (2017)Implementation of a fault-tolerant, globally-asynchronous-locally-synchronous, inter-chip NoC communication bridge on FPGAs., , and . NORCAS, page 1-6. IEEE, (2017)Artificial neural network emulation on NOC based multi-core FPGA platform., , and . NORCHIP, page 1-4. IEEE, (2012)Grammar-based design of embedded systems., , , , and . J. Syst. Archit., 47 (3-4): 225-240 (2001)A Markovian Approach for Detecting Failures in the Xilinx SEM core., and . FPT, page 1-4. IEEE, (2022)An Object-Oriented Concept for Intelligent Library Functions., , and . VLSI Design, page 355-358. IEEE Computer Society, (1998)Synthesis of VLIW Accelerators from Formal Descriptions in a Real-Time Multi-Core Environment.. FPGAworld, page 23-29. ACM, (2017)Simulation and Analysis of Embedded DSP Systems Using Petri Nets., , and . IEEE International Workshop on Rapid System Prototyping, page 64-70. IEEE Computer Society, (2003)A formal, model-driven design flow for system simulation and multi-core implementation., , , , , and . SIES, page 254-263. IEEE, (2015)