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Introduction to the Special Section on the 2018 IEEE BCICTS Conference.. IEEE J. Solid State Circuits, 54 (9): 2359-2360 (2019)Hardware reduction by combining pipelined A/D conversion and FIR filtering for channel equalization., and . ISCAS (3), page 489-492. IEEE, (2004)A fully integrated scalable W-band phased-array module with integrated antennas, self-alignment and self-test., , , , and . ISSCC, page 74-76. IEEE, (2018)A 35-GS/s, 4-Bit Flash ADC With Active Data and Clock Distribution Trees., , and . IEEE J. Solid State Circuits, 44 (6): 1709-1720 (2009)Design of a Dual W- and D-Band PLL., , , , , , and . IEEE J. Solid State Circuits, 46 (5): 1011-1022 (2011)Introduction to the Special Section on the 2015 Compound Semiconductor Integrated Circuit Symposium.. IEEE J. Solid State Circuits, 51 (9): 2015-2016 (2016)Introduction to the Special Section on the 2017 IEEE BCTM and IEEE CSICS Conferences., and . IEEE J. Solid State Circuits, 53 (9): 2439-2440 (2018)A Fully Integrated 384-Element, 16-Tile, $W$ -Band Phased Array With Self-Alignment and Self-Test., , , and . IEEE J. Solid State Circuits, 54 (9): 2419-2434 (2019)A 30-GS/sec Track and Hold Amplifier in 0.13-μm CMOS Technology., , and . CICC, page 493-496. IEEE, (2006)A 70-100 GHz Direct-Conversion Transmitter and Receiver Phased Array Chipset Demonstrating 10 Gb/s Wireless Link., , , and . IEEE J. Solid State Circuits, 48 (5): 1113-1125 (2013)