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Adaptive ILP control to increase fault tolerance for VLIW processors.

, , and . ASAP, page 9-16. IEEE Computer Society, (2016)

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ISA-DTMR: Selective Protection in Configurable Heterogeneous Multicores., , , , , and . ARC, volume 10824 of Lecture Notes in Computer Science, page 231-242. Springer, (2018)Design space exploration for PIM architectures in 3D-stacked memories., , , , and . CF, page 113-120. ACM, (2018)Adaptive ILP control to increase fault tolerance for VLIW processors., , and . ASAP, page 9-16. IEEE Computer Society, (2016)Exploiting Idle Hardware to Provide Low Overhead Fault Tolerance for VLIW Processors., , , , , and . JETC, 13 (2): 13:1-13:21 (2016)Run-time phase prediction for a reconfigurable VLIW processor., , , , , and . DATE, page 1634-1639. IEEE, (2016)Exploiting Reconfigurable Vector Processing for Energy-Efficient Computation in 3D-Stacked Memories., , , , , and . ARC, volume 11444 of Lecture Notes in Computer Science, page 262-276. Springer, (2019)Adaptive and polymorphic VLIW processor to optimize fault tolerance, energy consumption, and performance., , , , and . CF, page 54-61. ACM, (2018)Enabling Near-Data Accelerators Adoption by Through Investigation of Datapath Solutions., , , , , and . Int. J. Parallel Program., 49 (2): 237-252 (2021)Generating Optimized Multicore Accelerator Architectures., , , and . SBESC, page 1-8. IEEE, (2019)Tuning the ISA for increased heterogeneous computation in MPSoCs., , and . DATE, page 1722-1727. IEEE, (2020)