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proprietary SoC with an ADPLL-based fast frequency offset compensation in 40nm CMOS.

Y. Liu, C. Bachmann, X. Wang, Y. Zhang, A. Ba, B. Busze, M. Ding, P. Harpe, G. van Schaik, G. Selimis, H. Giesen, J. Gloudemans, A. Sbai, L. Huang, H. Kato, G. Dolmans, K. Philips, and H. de Groot. ISSCC, page 1-3. IEEE, (2015)

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Sebastian Philips

Heinz Philips

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Jürgen Philips

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Design and built-in characterization of digital-to-time converters for ultra-low power ADPLLs.P. Chen, X. Huang, Y. Liu, M. Ding, C. Zhou, A. Ba, K. Philips, H. de Groot, and R. Staszewski. ESSCIRC, page 283-286. IEEE, (2015)A 1.6mW 0.5GHz open-loop VGA with fast startup and offset calibration for UWB radios.P. Harpe, C. Zhou, K. Philips, and H. de Groot. ESSCIRC, page 103-106. IEEE, (2011)A 10.7-MHz IF-to-baseband ΣΔ A/D conversion system for AM/FM radio receivers.E. van der Zwan, K. Philips, and C. Bastiaansen. IEEE J. Solid State Circuits, 35 (12): 1810-1819 (2000)A 2.4 GHz ULP OOK Single-Chip Transceiver for Healthcare Applications.M. Vidojkovic, X. Huang, P. Harpe, S. Rampu, C. Zhou, L. Huang, J. van de Molengraft, K. Imamura, B. Busze, F. Bouwens and 7 other author(s). IEEE Trans. Biomed. Circuits Syst., 5 (6): 523-534 (2011)An Ultra-Low Power 1.7-2.7 GHz Fractional-N Sub-Sampling Digital Frequency Synthesizer and Modulator for IoT Applications in 40 nm CMOS.Y. Liu, J. van den Heuvel, T. Kuramochi, B. Busze, P. Mateman, V. Chillara, B. Wang, R. Staszewski, and K. Philips. IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (5): 1094-1105 (2017)9.8 An 860μW 2.1-to-2.7GHz all-digital PLL-based frequency modulator with a DTC-assisted snapshot TDC for WPAN (Bluetooth Smart and ZigBee) applications.V. Chillara, Y. Liu, B. Wang, A. Ba, M. Vidojkovic, K. Philips, H. de Groot, and R. Staszewski. ISSCC, page 172-173. IEEE, (2014)A circuit-design-driven tool with a hybrid automation approach for SAR ADCs in IoT.M. Ding, G. Chen, P. Harpe, B. Busze, Y. Liu, C. Bachmann, K. Philips, and A. van Roermund. DATE, page 672-675. IEEE, (2018)24.7 A 673µW 1.8-to-2.5GHz dividerless fractional-N digital PLL with an inherent frequency-capture capability and a phase-dithering spur mitigation for IoT applications.Y. He, Y. Liu, T. Kuramochi, J. van den Heuvel, B. Busze, N. Markulic, C. Bachmann, and K. Philips. ISSCC, page 420-421. IEEE, (2017)A 8mW-RX/113mW-TX, Sub-GHz SoC with time-dithered PA ramping for LPWAN applications.H. Gul, J. Romme, P. Mateman, J. Dijkhuis, X. Huang, C. Zhou, B. Busze, G. van Schaik, E. Bechthum, M. Ding and 5 other author(s). ESSCIRC, page 376-379. IEEE, (2017)A high-band IR-UWB chipset for real-time duty-cycled communication and localization systems.X. Wang, K. Philips, C. Zhou, B. Busze, H. Pflug, A. Young, J. Romme, P. Harpe, S. Bagga, S. D'Amico and 3 other author(s). A-SSCC, page 381-384. IEEE, (2011)

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Disambiguation of "Philips, Kathleen"

Please choose a person to relate this publication to

Sebastian Philips

Heinz Philips

Rosa Philips

Josef Philips

Jürgen Philips

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Philips, Kathleen"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 13.2 A 3.7mW-RX 4.4mW-TX fully integrated Bluetooth Low-Energy/IEEE802.15.4/proprietary SoC with an ADPLL-based fast frequency offset compensation in 40nm CMOS.

Please choose a person to relate this publication to

Sebastian Philips

Heinz Philips

Rosa Philips

Josef Philips

Jürgen Philips

Other publications of authors with the same name

Disambiguation