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Reconfigurable Architecture for Base-band Data Processing., , and . PDPTA, CSREA Press, (2000)NoC Based Distributed Partitionable Memory System for a Coarse Grain Reconfigurable Architecture., , , and . VLSI Design, page 232-237. IEEE Computer Society, (2011)Generating high tail accuracy Gaussian Random Numbers in hardware using central limit theorem., , , and . VLSI-SoC, page 60-65. IEEE, (2011)Flexible Codesign Target Architecture for Early Prototyping of CMIST Systems., , and . FPL, volume 1142 of Lecture Notes in Computer Science, page 193-199. Springer, (1996)Refresh Triggered Computation: Improving the Energy Efficiency of Convolutional Neural Network Accelerators., , , and . CoRR, (2019)SPEED: Open-Source Framework to Accelerate Speech Recognition on Embedded GPUs., , and . DSD, page 94-101. IEEE Computer Society, (2017)Morphable Compression Architecture for Efficient Configuration in CGRAs., , , , , , , and . DSD, page 42-49. IEEE Computer Society, (2014)Test Strategies on Functionally Partitioned Module-Based Programmable Architecture for Base-Band Processing., , and . DSD, page 326-335. IEEE Computer Society, (2001)The Rugby Model: A Conceptual Frame for the Study of Modelling, Analysis and Synthesis Concepts of Electronic Systems., , and . DATE, page 256-262. IEEE Computer Society / ACM, (1999)A Coarse Grain Reconfigurable Architecture for sequence alignment problems in bio-informatics., and . SASP, page 50-57. IEEE Computer Society, (2010)