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An Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled CMOS Circuits Based on Loading Effect.

, , , and . VLSI Design, page 583-588. IEEE Computer Society, (2007)

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An Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled CMOS Circuits Based on Loading Effect., , , and . VLSI Design, page 583-588. IEEE Computer Society, (2007)Special session 12C: Young professionals in test - Town meeting., , and . VTS, page 1. IEEE Computer Society, (2014)A study on impact of aggressor de-rating in the context of multiple crosstalk effects in circuits., , and . ACM Great Lakes Symposium on VLSI, page 529-534. ACM, (2009)A Pattern Generation Technique for Maximizing Switching Supply Currents Considering Gate Delays., , and . IEEE Trans. Computers, 61 (7): 986-998 (2012)On Modeling and Testing of Lithography Related Open Faults in Nano-CMOS Circuits., , and . DATE, page 616-621. ACM, (2008)BIST to Detect and Characterize Transient and Parametric Failures., , and . IEEE Des. Test Comput., 27 (5): 50-59 (2010)A Pattern Generation Technique for Maximizing Power Supply Currents., , and . ICCD, page 338-343. IEEE, (2006)Accelerating Soft Error Rate Testing Through Pattern Selection., , and . IOLTS, page 191-193. IEEE Computer Society, (2007)A study on impact of loading effect on capacitive crosstalk noise., , and . ISQED, page 696-701. IEEE Computer Society, (2009)Special session 12C: Town-hall meeting "young professionals in test"., and . VTS, page 1. IEEE Computer Society, (2013)