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6.2 A 60Gb/s 288mW NRZ transceiver with adaptive equalization and baud-rate clock and data recovery in 65nm CMOS technology.

J. Han, Y. Lu, N. Sutardja, and E. Alon. ISSCC, page 112-113. IEEE, (2017)

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Luyang Han

Mei Han

Muxin Han

Bing Han

Johannes Han

Other publications of authors with the same name

A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET.J. Im, D. Freitas, A. Roldan, R. Casey, S. Chen, A. Chou, T. Cronin, K. Geary, S. McLeod, L. Zhou and 7 other author(s). IEEE J. Solid State Circuits, 52 (12): 3486-3502 (2017)A Generated 7GS/s 8b Time-Interleaved SAR ADC with 38.2dB SNDR at Nyquist in 16nm CMOS FinFET.J. Han, E. Chang, S. Bailey, Z. Wang, W. Bae, A. Wang, N. Narevsky, A. Whitcombe, P. Lu, B. Nikolic and 1 other author(s). CICC, page 1-4. IEEE, (2019)A 32-Gb/s High-Swing PAM-4 Current-Mode Driver with Current-Bleeding Cascode Technique and Capacitive-Coupled Pre-drivers in 40-nm CMOS for Short-Reach Wireline Communications.E. Song, J. Yang, S. Hong, and J. Han. MWSCAS, page 1-4. IEEE, (2022)Non-blind Image Deconvolution using Sampling without Replacement.J. Han, J. Kim, and M. Kang. Image Processing: Algorithms and Systems, page 125-130. Society for Imaging Science and Technology, (2017)Analysis of Grounded Coplanar Waveguide (GCPW) for High-Speed Links Channel.Y. Oh, T. Sim, and J. Han. ISOCC, page 117-118. IEEE, (2023)A Variation-Tolerant Voltage-Mode Transmitter With 3+1 Tap FFE in 28-nm CMOS.W. Shin, H. Seo, S. Lee, D. Choi, Y. Kwak, S. Won, and J. Han. IEEE Trans. Circuits Syst. II Express Briefs, 71 (4): 1819-1823 (April 2024)BAG2: A process-portable framework for generator-based AMS circuit design.E. Chang, J. Han, W. Bae, Z. Wang, N. Narevsky, B. Nikolic, and E. Alon. CICC, page 1-8. IEEE, (2018)Automatic prior selection for image deconvolution: Statistical modeling on natural images.H. Lee, J. Han, S. Hong, and M. Kang. Signal Process., (2021)Multi-Frame Depth Super-Resolution for ToF Sensor With Total Variation Regularized L1 Function.J. Kim, J. Han, and M. Kang. IEEE Access, (2020)An Automated Design Methodology for Ring Voltage-Controlled Oscillators in Nanometer CMOS Technologies.D. Lee, G. Park, J. Han, and M. Choo. IEEE Access, (2023)

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Disambiguation of "Han, Jaeduk"

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6.2 A 60Gb/s 288mW NRZ transceiver with adaptive equalization and baud-rate clock and data recovery in 65nm CMOS technology.

Please choose a person to relate this publication to

Luyang Han

Mei Han

Muxin Han

Bing Han

Johannes Han

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Han, Jaeduk"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 6.2 A 60Gb/s 288mW NRZ transceiver with adaptive equalization and baud-rate clock and data recovery in 65nm CMOS technology.

Please choose a person to relate this publication to

Luyang Han

Mei Han

Muxin Han

Bing Han

Johannes Han

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
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APA
Chicago
DIN 1505
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6.2 A 60Gb/s 288mW NRZ transceiver with adaptive equalization and baud-rate clock and data recovery in 65nm CMOS technology.