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Disambiguation of "Kulkarni, Niranjan"

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A Clock Skewing Strategy to Reduce Power and Area of ASIC Circuits.

, , and . DAC, page 67:1-67:6. ACM, (2017)

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Niranjan Talukder

Jagadish Kulkarni

Niranjan Suri

Praveen Kulkarni

Niranjan Rajdev

 

Other publications of authors with the same name

Digital IP Protection Using Threshold Voltage Control., , , , and . CoRR, (2016)A Clock Skewing Strategy to Reduce Power and Area of ASIC Circuits., , and . DAC, page 67:1-67:6. ACM, (2017)A Novel Approach to Cell Formation., , and . ICFCA, volume 5548 of Lecture Notes in Computer Science, page 210-223. Springer, (2009)Integration of threshold logic gates with RRAM devices for energy efficient and robust operation., , , and . NANOARCH, page 39-44. IEEE Computer Society/ACM, (2014)Spintronic threshold logic array (STLA) - a compact, low leakage, non-volatile gate array architecture., , and . NANOARCH, page 188-195. ACM, (2012)Dynamic and leakage power reduction of ASICs using configurable threshold logic gates., , , , and . CICC, page 1-4. IEEE, (2015)Spintronic Threshold Logic Array (STLA) - A compact, low leakage, non-volatile gate array architecture., , and . J. Parallel Distributed Comput., 74 (6): 2452-2460 (2014)A New Approach to Clock Skewing for Area and Power Optimization of ASICs Using Differential Flipflops and Local Clocking., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (11): 4164-4176 (November 2023)Fast and robust differential flipflops and their extension to multi-input threshold gates., , , and . ISCAS, page 822-825. IEEE, (2015)A fast, energy efficient, field programmable threshold-logic array., , and . FPT, page 300-305. IEEE, (2014)