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Designing and Validating Process-Variation-Aware Cell Libraries., , , and . ISQED, page 761-770. IEEE Computer Society, (2007)An Architectural Power Optimization Case Study using High-level Synthesis., and . ICCD, page 562-570. IEEE Computer Society, (1997)CHOP: A Constraint-Driven System-Level Partitioner., and . DAC, page 514-519. ACM, (1991)Analysis of emerging core-based design lifecycle.. ICCAD, page 445-449. ACM / IEEE Computer Society, (1998)High-level scheduling model and control synthesis for a broad range of design applications., and . ICCAD, page 236-243. IEEE Computer Society / ACM, (1997)Architectural Rule Checking for High-level Synthesis., , and . DATE, page 949-950. IEEE Computer Society, (1998)Exploiting Setup-Hold-Time Interdependence in Static Timing Analysis., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (6): 1114-1125 (2007)An ASIP design methodology for embedded systems.. CODES, page 17-21. ACM, (1999)Pessimism Reduction In Static Timing Analysis Using Interdependent Setup and Hold Times., , , , and . ISQED, page 159-164. IEEE Computer Society, (2006)Data Path Tradeoffs Using MABAL., and . DAC, page 511-516. IEEE Computer Society Press, (1990)