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Disambiguation of "Jayaram, Vinay"

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Multi-task logistic regression in brain-computer interfaces.

, , , and . SMC, page 2307-2312. IEEE, (2016)

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Vittalapura Jayaram

Jayaram Dadda

Vinay Suryaprakash

Vinay Bettadapura

Vinay Vijayakumar

 

Other publications of authors with the same name

Timing-based delay test for screening small delay defects., , and . DAC, page 320-325. ACM, (2006)2021 BEETL Competition: Advancing Transfer Learning for Subject Independence & Heterogenous EEG Data Sets., , , , , , , , , and 11 other author(s). CoRR, (2022)A Cognitive Brain-Computer Interface for Patients with Amyotrophic Lateral Sclerosis., , , , , , , , , and . SMC, page 3187-3191. IEEE, (2015)Frequency peak features for low-channel classification in motor imagery paradigms., , and . NER, page 321-324. IEEE, (2017)Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design., , and . DAC, page 533-538. IEEE, (2007)A novel framework for faster-than-at-speed delay test considering IR-drop effects., , and . ICCAD, page 198-203. ACM, (2006)Supply Voltage Noise Aware ATPG for Transition Delay Faults., , and . VTS, page 179-186. IEEE Computer Society, (2007)MOABB: Trustworthy algorithm benchmarking for BCIs., and . CoRR, (2018)ArmSym: A Virtual Human-Robot Interaction Laboratory for Assistive Robotics., , , , and . IEEE Trans. Hum. Mach. Syst., 51 (6): 568-577 (2021)2021 BEETL Competition: Advancing Transfer Learning for Subject Independence & Heterogenous EEG Data Sets., , , , , , , , , and 11 other author(s). NeurIPS (Competition and Demos), volume 176 of Proceedings of Machine Learning Research, page 205-219. PMLR, (2021)