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Disambiguation of "Sim, Jae-Yoon"

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Digital-domain calibration of split-capacitor DAC with no extra calibration DAC for a differential-type SAR ADC.

, , , and . A-SSCC, page 77-80. IEEE, (2011)

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Jae-Han Sim

Jae-Yoon Kim

Unyong Sim

Sim Hägele

Gavin Sim

 

Other publications of authors with the same name

45pW ESD clamp circuit for ultra-low power applications., , , , , and . CICC, page 1-4. IEEE, (2013)A Digitally Controlled Op-Amp with Level-Crossing-Based Approximation and its Application to a 10-bit Pipeline ADC., , , and . Journal of Circuits, Systems, and Computers, 25 (12): 1650155:1-1650155:16 (2016)A 650Mb/s-to-8Gb/s referenceless CDR circuit with automatic acquisition of data rate., , , , , and . ISSCC, page 184-185. IEEE, (2009)An 8GB/s quad-skew-cancelling parallel transceiver in 90nm CMOS for high-speed DRAM interface., , , , , , , and . ISSCC, page 136-138. IEEE, (2012)A 3.2Gb/s 8b Single-Ended Integrating DFE RX for 2-Drop DRAM Interface with Internal Reference Voltage and Digital Calibration., , , , , and . ISSCC, page 112-113. IEEE, (2008)5.5 A quadrature relaxation oscillator with a process-induced frequency-error compensation loop., , , , and . ISSCC, page 94-95. IEEE, (2017)Deadzone-Minimized Systematic Offset-Free Phase Detectors., , , and . IEICE Trans. Electron., 91-C (9): 1525-1528 (2008)An Analysis and Design Methodology of Resistor-Based Phase Error Averaging for Multiphase Generation., , , and . IEICE Trans. Electron., 93-C (12): 1662-1669 (2010)An 8.8-GS/s 6-bit CMOS Time-Interleaved Flash Analog-to-Digital Converter with Multi-Phase Clock Generator., , , , and . IEICE Trans. Electron., 90-C (6): 1156-1164 (2007)A QDR-Based 6-GB/s Parallel Transceiver With Current-Regulated Voltage-Mode Output Driver and Byte CDR for Memory Interface., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 60-II (2): 91-95 (2013)