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A 0.5-9.5-GHz, 1.2-µs Lock-Time Fractional-N DPLL With ±1.25%UI Period Jitter in 16-nm CMOS for Dynamic Frequency and Core-Count Scaling.

, , , , , , , and . IEEE J. Solid State Circuits, 52 (1): 21-32 (2017)

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