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Disambiguation of "Fujimori, Ichiro"

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A 0.5-9.5-GHz, 1.2-µs Lock-Time Fractional-N DPLL With ±1.25%UI Period Jitter in 16-nm CMOS for Dynamic Frequency and Core-Count Scaling.

, , , , , , , and . IEEE J. Solid State Circuits, 52 (1): 21-32 (2017)

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Temmyo Ichiro

Ichiro Yamaguchi

Yuichi Fujimori

Ichiro Yamaguchi

Ichiro Tamura

 

Other publications of authors with the same name

19.1 A 0.5-to-9.5GHz 1.2µs-lock-time fractional-N DPLL with ±1.25% UI period jitter in 16nm CMOS for dynamic frequency and core-count scaling in SoC., , , , , , , and . ISSCC, page 324-325. IEEE, (2016)A 2.7 GHz to 7 GHz Fractional-N LC-PLL Utilizing Multi-Metal Layer SoC Technology in 28 nm CMOS., , , , , , and . IEEE J. Solid State Circuits, 50 (4): 856-866 (2015)F1: High-speed interleaved ADCs., , , and . ISSCC, page 1-2. IEEE, (2015)F4: Emerging short-reach and high-density interconnect solutions for internet of everything., , , , , and . ISSCC, page 502-505. IEEE, (2016)A fully integrated SONET OC-48 transceiver in standard CMOS., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 36 (12): 1964-1973 (2001)A 0.5-9.5-GHz, 1.2-µs Lock-Time Fractional-N DPLL With ±1.25%UI Period Jitter in 16-nm CMOS for Dynamic Frequency and Core-Count Scaling., , , , , , , and . IEEE J. Solid State Circuits, 52 (1): 21-32 (2017)Session 7 overview: Optical transceivers and silicon photonics., and . ISSCC, page 114-115. IEEE, (2013)A 2.7GHz to 7GHz fractional-N LCPLL utilizing multimetal layer SoC technology in 28nm CMOS., , , , , , and . VLSIC, page 1-2. IEEE, (2014)A 5-V single-chip delta-sigma audio A/D converter with 111 dB dynamic range., , , , and . IEEE J. Solid State Circuits, 32 (3): 329-336 (1997)A multibit delta-sigma audio DAC with 120-dB dynamic range., , and . IEEE J. Solid State Circuits, 35 (8): 1066-1073 (2000)