( en | de | ru )

 

Disambiguation of "Asifuzzaman, Kazi"

Author of the publication

copydeleteadd this publication to your clipboard
Performance Impact of a Slower Main Memory: A case study of STT-MRAM in HPC.

, , , , , , and . MEMSYS, page 40-49. ACM, (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Svetlana Kazitsyna

Ahmad Kazimi

Emmanuel Owden Kazimoto

Julian Kazin

Amin Hasan Kazi

 

Other publications of authors with the same name

Main memory latency simulation: the missing link., , , , , and . MEMSYS, page 107-116. ACM, (2018)Evaluating HPC Kernels for Processing in Memory., , , and . MEMSYS, page 1:1-1:6. ACM, (2022)HPC Benchmarking: Scaling Right and Looking Beyond the Average., , , , and . Euro-Par, volume 11014 of Lecture Notes in Computer Science, page 135-146. Springer, (2018)Performance and Power Estimation of STT-MRAM Main Memory with Reliable System-level Simulation., , and . ACM Trans. Embed. Comput. Syst., 21 (1): 6:1-6:25 (2022)Enabling a reliable STT-MRAM main memory simulation., , and . MEMSYS, page 283-292. ACM, (2017)A Novel Scalable Array Design for III-V Compound Semiconductor-based Nonvolatile Memory (UltraRAM) with Separate Read-Write Paths., , and . ISQED, page 1-7. IEEE, (2023)CMOS-based Single-Cycle In-Memory XOR/XNOR., , , , and . CoRR, (2023)Evaluation of STT-MRAM main memory for HPC and real-time systems.. Polytechnic University of Catalonia, Spain, (2019)The UP2DATE Baseline Research Platforms., , , , , , , , and . DATE, page 1340-1343. IEEE, (2021)STT-MRAM for real-time embedded systems: performance and WCET implications., , , , and . MEMSYS, page 195-205. ACM, (2019)