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Disambiguation of "Makosiej, Adam"

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TFET NDR skewed inverter based sensing method.

, , , , , and . NANOARCH, page 13-14. ACM, (2016)

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Adam Jakiemiw

Adam Zomotor

Olaf Adam

Karlheinz Adam

Elke Adam

 

Other publications of authors with the same name

CMOS SRAM scaling limits under optimum stability constraints., , , and . ISCAS, page 1460-1463. IEEE, (2013)SRAM Voltage and Current Sense Amplifiers in sub-32nm Double-gate CMOS Insensitive to Process Variations and Transistor Mismatch., , , , and . ISCAS, page 3170-3173. IEEE, (2009)SamurAI: A 1.7MOPS-36GOPS Adaptive Versatile IoT Node with 15, 000× Peak-to-Idle Power Reduction, 207ns Wake-Up Time and 1.3TOPS/W ML Efficiency., , , , , , , , , and 11 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)Sub-picowatt retention mode TFET memory for CMOS sensor processing nodes., , , , and . IWASI, page 266-270. IEEE, (2015)TFET NDR skewed inverter based sensing method., , , , , and . NANOARCH, page 13-14. ACM, (2016)Energy-Efficient 4T SRAM Bitcell with 2T Read-Port for Ultra-Low-Voltage Operations in 28 nm 3D Monolithic CoolCubeTM Technology., , , , , , , , , and . NANOARCH, page 131-137. ACM, (2018)16Kb hybrid TFET/CMOS reconfigurable CAM/SRAM array based on 9T-TFET bitcell., , , , and . ESSDERC, page 356-359. IEEE, (2016)An innovative sub-32nm SRAM voltage sense amplifier in double-gate CMOS insensitive to process variations and transistor mismatch., , , , and . ICECS, page 554-557. IEEE, (2008)1.56GHz/0.9V energy-efficient reconfigurable CAM/SRAM using 6T-CMOS bitcell., , , , and . ESSCIRC, page 316-319. IEEE, (2017)Tunnel FET based ultra-low-leakage compact 2T1C SRAM., , , , and . ISQED, page 71-75. IEEE, (2017)