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Disambiguation of "Chou, Hong-Ru"

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48-Mode Reconfigurable Design of SDF FFT Hardware Architecture Using Radix-32 and Radix-23 Design Approaches.

, , and . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (6): 1456-1467 (2017)

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Remi Chou

Joseph Chou

Ru Zhang

Ru Xie

Maria Chou

 

Other publications of authors with the same name

Flexible design and implementation of QC-Based LDPC decoder architecture for on-line user-defined matrix downloading and efficient decoding., and . Integr., (2019)Reconfigurable VLSI design of processing kernel for multiple-radix single-path delay feedback FFT systems., , and . GCCE, page 1-2. IEEE, (2016)Design and Implementation of Flexible and Reconfigurable SDF-Based FFT Chip Architecture With Changeable-Radix Processing Elements., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (11): 3942-3955 (2018)VLSI Design and Implementation of Reconfigurable 46-Mode Combined-Radix-Based FFT Hardware Architecture for 3GPP-LTE Applications., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (1): 118-129 (2018)48-Mode Reconfigurable Design of SDF FFT Hardware Architecture Using Radix-32 and Radix-23 Design Approaches., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (6): 1456-1467 (2017)Reconfigurable VLSI design of a changeable hybrid-radix FFT hardware architecture with 2D-FIFO storing structure for 3GPP LTE systems., and . ICT Express, 4 (3): 144-148 (2018)Reconfigurable hardware design of low-area-cost computing kernel engine for different radixes of single-path delay feedback FFT systems., and . ICCE, page 418-419. IEEE, (2017)VLSI design and implementation of a reconfigurable hardware-friendly Polar encoder architecture for emerging high-speed 5G system., , and . Integr., (2018)A 2-D grouping FIFO based hardware architecture for supporting 36-mode hybrid-radix FFT design in 3GPP-LTE systems., and . GCCE, page 1-2. IEEE, (2017)