( en | de | ru )

 

Disambiguation of "Iizuka, Tetsuya"

Author of the publication

copydeleteadd this publication to your clipboard
Experimental demonstration of stochastic comparators for fine resolution ADC without calibration.

, , , , and . ICECS, page 29-32. IEEE, (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Tetsuya Takahashi

Hajime Iizuka

Tetsuya Mizutani

Tetsuya Kawata

Tetsuya Takahashi

 

Other publications of authors with the same name

High-resolution measurement of magnetic field generated from cryptographic LSIs., , , , , and . SAS, page 111-114. IEEE, (2014)Mining sequential patterns including time intervals., , , and . Data Mining and Knowledge Discovery: Theory, Tools, and Technology, volume 4057 of SPIE Proceedings, page 213-220. SPIE, (2000)A Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion., , , and . VLSI-SoC, page 55-58. IEEE, (2018)All-digital PMOS and NMOS process variability monitor utilizing buffer ring with pulse counter., , , , and . ASP-DAC, page 79-80. IEEE, (2011)Experimental demonstration of stochastic comparators for fine resolution ADC without calibration., , , , and . ICECS, page 29-32. IEEE, (2016)A Gate Delay Mismatch Tolerant Time-Mode Analog Accumulator Using a Delay Line Ring., , , and . IEICE Trans. Electron., 100-C (9): 736-745 (2017)Cascaded Time Difference Amplifier with Differential Logic Delay Cell., , , , and . IEICE Trans. Electron., 94-C (4): 654-662 (2011)Exact Minimum-Width Transistor Placement for Dual and Non-dual CMOS Cells., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 88-A (12): 3485-3491 (2005)All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter., , , , and . IEICE Trans. Electron., 94-C (4): 487-494 (2011)11 Gb/s 140 GHz OOK modulator with 24.6 dB isolation utilising cascaded switch and amplifier-based stages in 65 nm bulk CMOS., , , , and . IET Circuits Devices Syst., 14 (3): 322-326 (2020)