( en | de | ru )

 

Disambiguation of "Hamzaoglu, Fatih"

Author of the publication

copydeleteadd this publication to your clipboard
Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache.

, , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 10 (2): 91-95 (2002)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Abdelhak Fatihi

Fatih Bayazit

Fatih Bilgili

Fatih Ceteci

Fatih Koyuncu

 

Other publications of authors with the same name

Circuit-level techniques to control gate leakage for sub-100nm CMOS., and . ISLPED, page 60-63. ACM, (2002)Multi-Phase 1 GHz Voltage Doubler Charge Pump in 32 nm Logic Process., , , , , , and . IEEE J. Solid State Circuits, 45 (4): 751-758 (2010)A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply., , , , , , , , and . IEEE J. Solid State Circuits, 41 (1): 146-151 (2006)A 4.2GHz 0.3mm2 256kb Dual-Vcc SRAM Building Block in 65nm CMOS., , , , , , , , , and 3 other author(s). ISSCC, page 2572-2581. IEEE, (2006)A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management., , , , , , , , and . ISSCC, page 456-457. IEEE, (2009)An offset-cancelling four-phase voltage sense amplifier for resistive memories in 14nm CMOS., , , and . CICC, page 1-4. IEEE, (2017)Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache., , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 10 (2): 91-95 (2002)A 1 Gb 2 GHz 128 GB/s Bandwidth Embedded DRAM in 22 nm Tri-Gate CMOS Technology., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 50 (1): 150-157 (2015)Gain-Cell CIM: Leakage and Bitline Swing Aware 2T1C Gain-Cell eDRAM Compute in Memory Design with Bitline Precharge DACs and Compact Schmitt Trigger ADCs., , , , and . VLSI Technology and Circuits, page 112-113. IEEE, (2022)16.2 eDRAM-CIM: Compute-In-Memory Design with Reconfigurable Embedded-Dynamic-Memory Array Realizing Adaptive Data Converters and Charge-Domain Computing., , , , , and . ISSCC, page 248-250. IEEE, (2021)