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Disambiguation of "Brisk, Philip"

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Matrix Profile II: Exploiting a Novel Algorithm and GPUs to Break the One Hundred Million Barrier for Time Series Motifs and Joins.

, , , , , , , and . ICDM, page 739-748. IEEE Computer Society, (2016)

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Rudolf Briske

Paul Brisken

Magnus Briskorn

Ana Briski

Kathrin Brisken

 

Other publications of authors with the same name

Path scheduling on digital microfluidic biochips., and . DAC, page 26-35. ACM, (2012)Reducing the pressure on routing resources of FPGAs with generic logic chains., , , and . FPGA, page 237-246. ACM, (2011)Reducing the cost of floating-point mantissa alignment and normalization in FPGAs., , , , , and . FPGA, page 255-264. ACM, (2012)Reducing Microfluidic Very Large Scale Integration (mVLSI) Chip Area by Seam Carving., , and . ACM Great Lakes Symposium on VLSI, page 459-462. ACM, (2017)A Low-Cost Field-Programmable Pin-Constrained Digital Microfluidic Biochip., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 33 (11): 1657-1670 (2014)Way Stealing: A Unified Data Cache and Architecturally Visible Storage for Instruction Set Extensions., , , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (1): 62-75 (2014)Compressor tree synthesis on commercial high-performance FPGAs., , , and . ACM Trans. Reconfigurable Technol. Syst., 4 (4): 39:1-39:19 (2011)An FPGA Logic Cell and Carry Chain Configurable as a 6: 2 or 7: 2 Compressor., , and . ACM Trans. Reconfigurable Technol. Syst., 2 (3): 19:1-19:42 (2009)MPSoC Design Using Application-Specific Architecturally Visible Communication., , , and . HiPEAC, volume 5409 of Lecture Notes in Computer Science, page 183-197. Springer, (2009)Exploiting fast carry-chains of FPGAs for designing compressor trees., , and . FPL, page 242-249. IEEE, (2009)