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16kbit 1T1R OxRAM arrays embedded in 28nm FDSOI technology demonstrating low BER, high endurance, and compatibility with core logic transistors., , , , , , , , , and 20 other author(s). IMW, page 1-4. IEEE, (2021)An Unbalanced Area Ratio Study for High Performance Monolithic 3D Integrated Circuits., , , and . ISVLSI, page 350-355. IEEE Computer Society, (2015)From 2D to monolithic 3D predictive design platform: An innovative migration methodology for benchmark purpose., , , , , , , , and . 3DIC, page 1-5. IEEE, (2016)Intermediate BEOL process influence on power and performance for 3DVLSI., , , , , , , and . 3DIC, page TS1.3.1-TS1.3.5. IEEE, (2015)Merging PDKs to Build a Design Environment for 3D Circuits: Methodology, Challenges and Limitations., , , , , , and . 3DIC, page 1-5. IEEE, (2019)Area and Cost Analysis of the Mixed Signal Circuits in a Novel Monolithic 3D Process., , , , and . MWSCAS, page 704-707. IEEE, (2021)Thermal performance of CoolCube™ monolithic and TSV-based 3D integration processes., , , , , , and . 3DIC, page 1-5. IEEE, (2016)3DCoB: A new design approach for Monolithic 3D Integrated circuits., , , and . ASP-DAC, page 79-84. IEEE, (2014)Impact of intermediate BEOL technology on standard cell performances of 3D VLSI., , , , , , , , , and 3 other author(s). ESSDERC, page 218-221. IEEE, (2016)A review on opportunities brought by 3D-monolithic integration for CMOS device and digital circuit., , , , , , , , and . ICICDT, page 141-144. IEEE, (2018)